Validation and Optimization of Analog Circuits using Randomized Search Algorithms

[pdf][Duplex]

My Ph.D. thesis, published by University of Illinois at Urbana-Champaign.

The thesis page and the abstract

Duplex Optimization

Duplex: Simultaneous Parameter-Performance Exploration for Optimizing Analog Circuits

[paper] – Proceedings of 2016 International Conference On Computer Aided Design (ICCAD), 2016

We present Duplex random tree search, an algorithm to optimize performance metrics of analog and mixed signal circuits. Duplex determines the optimal design, the Pareto set and the sensitivity of circuit’s performance metrics to its parameters. We demonstrate that Duplex is 5× faster than the state-of-the-art and finds the global optimum for a design whose previously published result was a local optimum. We show our algorithm’s scalability by optimizing a system-level post-layout charged-pump PLL circuit.

A Random Tree Search Algorithm for Nash Equilibrium in Capacitated Selfish Replication Games

[paper][source] – Proceedings of IEEE 55th Conference on Decision and Control (CDC), 2016

In this paper, we consider a resource allocation game with binary preferences and limited capacities over large scale networks and propose a novel randomized algorithm for searching its pure-strategy Nash equilibrium points. It is known that such games always admit a pure-strategy Nash equilibrium and benefit from having a low price of anarchy. However, the best known theoretical results only provide a quasi-polynomial constant approximation algorithm of the equilibrium points over general networks. Here, we search the state space of the resource allocation game for its equilibrium points. We use a random tree based search method to minimize a proper score function and direct the search toward the pure-strategy Nash equilibrium points of the system. We demonstrate efficiency of our algorithm through some empirical results.

Analog Test Compression

[pdf] – Published in Elsevier VLSI integration journal, 2016.

Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression for electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find the minimum for these computationally hard integrals, which corresponds to the optimally compressed analog test. We demonstrate with an op-amp, VCO, and CMOS inverter that the method consistently reduces the length of each test by an average of 93%. Our technology can compress tests in the presence of process variation and utilize parallel processing to speed up the compression algorithm.

Every Test Makes a Difference: Compressing Analog Tests to Decrease Production Costs

[pdf] –Proceedings of 21st Asia and South Pacific Design Automation Conference (ASP-DAC 2016), 2016.

Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost.
We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functionals of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by 93%.

A Novel Test Compression Algorithm for Analog Circuits to Decrease Production Costs

                                       

2016

Journal Articles

Ahmadyan, Seyed Nematollah; Natarajan, Suriyaprakash; Vasudevan, Shobha

A Novel Test Compression Algorithm for Analog Circuits to Decrease Production Costs Journal Article

Elsevier VLSI integration, 2016.

Abstract | BibTeX | Tags: Analog, optimization, random tree, simulation, Test generation

Conferences

Ahmadyan, Seyed Nematollah; Etesami, Seyed Rasoul; Poor, Vincent H

A Random Tree Search Algorithm for Nash Equilibrium in Capacitated Selfish Replication Games Conference

55th IEEE Conference on Decision and Control, 2016.

BibTeX | Tags: game theory, optimization, random tree

Ahmadyan, Seyed Nematollah; Vasudevan, Shobha

Duplex: Simultaneous Parameter-Performance Exploration for Optimizing Analog Circuits Conference

Proceedings of 2016 International Conference On Computer Aided Design (ICCAD), 2016.

BibTeX | Tags: Analog, optimization, random tree

Ahmadyan, Seyed Nematollah; Vasudevan, Shobha; Natarajan, Suriyaprakash

Every Test Makes a Difference: Compressing Analog Tests to Decrease Production Costs Conference

Proceedings of 21st Asia and South Pacific Design Automation Conference (ASP-DAC 2016), 2016.

Abstract | BibTeX | Tags: Analog, optimization, random tree, Test generation

PhD Theses

Ahmadyan, Seyed Nematollah

Validation and Optimization of Analog Circuits using Randomized Search Algorithms PhD Thesis

2016.

Links | BibTeX | Tags: optimization

2015

Journal Articles

Ahmadyan, Seyed Nematollah; Vasudevan, Shobha

Automated Transient Input Stimuli Generation for Analog Circuits Journal Article

IEEE Transaction on Computer Aided Design (TCAD), 2015.

Abstract | Links | BibTeX | Tags: Analog, random tree, simulation, Test generation

Conferences

Ahmadyan, Seyed Nematollah; Vasudevan, Shobha; Chiprout, Eli; Gu, Chenjie; Natarajan, Suriyaprakash

Fast Eye Diagram Analysis For High-Speed IO Circuits (Best paper nomination) Conference

Proceedings of 2015 Design, Automation and Test in Europe (DATE), 2015, ISBN: 978-3-9815370-4-8.

Abstract | Links | BibTeX | Tags: Analog, eye diagram, random tree, signal integrity, simulation

2014

Journal Articles

Kumar, Jayanand Asok; Ahmadyan, Seyed Nematollah; Vasudevan, Shobha

Efficient Statistical Model Checking of Hardware Circuits with Multiple Failure Regions Journal Article

IEEE Transaction on Computer Aided Design, 33 (6), 2014.

Abstract | Links | BibTeX | Tags: Analog, Model Checking, Verification

2013

Conferences

Ahmadyan, Seyed Nematollah; Vasudevan, Shobha

Rapidly-exploring random forests: algorithms and applications in formal verification of nonlinear analog circuits Conference

workshop of Frontiers in Analog Circuits (FAC), 2013.

BibTeX | Tags: Analog, random tree

Ahmadyan, Seyed Nematollah; Vasudevan, Shobha

Reachability Analysis of Nonlinear Analog Circuits through Iterative Reachable Set Reduction Conference

Proceedings of the IEEE/ACM International Conference on Design, Automation and Test in Europe (DATE), 2013.

BibTeX | Tags: Analog, Reachability Analysis, Verification

Ahmadyan, Seyed Nematollah; Kumar, Jayanand Asok; Vasudevan, Shobha

Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm Conference

Proceedings of the IEEE/ACM International Conference on Design, Automation and Test in Europe (DATE), 2013.

BibTeX | Tags: Analog, Logic, random tree, runtime monitoring

Ahmadyan, Seyed Nematollah; Vasudevan, Shobha

Efficient Stochastic SAT Solving Using Random Graphs (Invited) Conference

workshop of Constrained Formal Verification, 2013.

BibTeX | Tags: optimization, random tree, SAT

Miscellaneous

Ahmadyan, Seyed Nematollah; Vasudevan, Shobha

Verification of Analog Circuits using Rapidly-exploring Random Trees Miscellaneous

Information Trust Institute Seminar series, 2013.

BibTeX | Tags: Analog, random tree, Verification

2012

Conferences

Ahmadyan, Seyed Nematollah; Kumar, Jayanand Asok; Vasudevan, Shobha

Goal-Oriented Stimulus Generation for Analog Circuits Conference

Proceedings of 49th Design Automation Conference (DAC), 2012.

BibTeX | Tags: Analog, random tree, Test generation

Ahmadyan, Seyed Nematollah; Fazeli, Mahdi; Farhadi, Nahid; Miremadi, Seyed Ghassem

Value-Aware Low Power Register File Architecture (Best Paper Award) Conference

Proceedings of the 16th symposium on Computer Architecture and Digital Systems (CADS), 2012.

BibTeX | Tags: Computer Architecture, low power, Register file

2011

Conferences

Fazeli, Mahdi; Ahmadyan, Seyed Nematollah; Miremadi, Seyed Ghassem; Asadi, Hossein; Tahoori, Mahdi Baradaran

Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs) Conference

2011.

BibTeX | Tags: reliability, Soft error

Masters Theses

Ahmadyan, Seyed Nematollah

Analytical approaches for soft-error rate estimation of digital circuits at circuit level Masters Thesis

Sharif university of technology, 2011.

BibTeX | Tags: Soft error

2010

Conferences

Fazeli, Mahdi; Miremadi, Seyed Ghassem; Asadi, Hossein; Ahmadyan, Seyed Nematollah

A Fast and Accurate Multi-cycle Soft Error Rate Estimation Approach to Resilient Embedded Systems Design Conference

Proceedings of the 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2010.

BibTeX | Tags: reliability, Soft error

Ahmadyan, Seyed Nematollah; Miremadi, Seyed Ghassem

Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A Conference

Proceedings of IEEE Behavioral Modeling and Simulation Conference (BMAS), 2010.

BibTeX | Tags: Analog, fault injection

2009

Masters Theses

Ahmadyan, Seyed Nematollah

Fault injection using behavioral model of faults (BS-thesis) Masters Thesis

Sharif University of technology, 2009.

BibTeX | Tags: fault injection

2008

Conferences

Fazeli, Mahdi; Ahmadyan, Seyed Nematollah; Miremadi, Seyed Ghassem

A Low Energy Soft Error-Tolerant Architecture for the Register File in Embedded Processors Conference

The 11th IEEE High Assurance Systems Engineering Symposium, 2008.

BibTeX | Tags: low power, Register file, reliability